On Ink Jet Print Heads Piezo-electric transducers are used to eject ink drops. Positive and negative voltages in particular waveforms are required for this purpose: the positive voltage to fill the orifices with the ink and the negative voltage to eject the ink drops. The shapes of such waveforms are determined by the type of the ink and the specific characteristics of the print heads. A Head Drive ASIC (HDA) is used to provide such waveforms. The amplitude of the output voltage across each transducer on the print head must be individually adjusted to compensate for sensitivity variations of different piezo-electric elements on the print heads. This is called “normalization” or “calibration”. In present Head Driver ASIC design, a digital method is used for normalization procedure. An alternate method can simplify the circuitry and improve the normalization accuracy.
A simplified block diagram of the circuitry used in prior art Head Driver ASIC and related signal waveforms are shown in FIGS. 1 and 2 respectively. VPP 10 and VSS 12 are the positive and the negative power supplies with voltages in particular shapes as shown. The piezo-electric transducer has a capacitive load and is shown by a capacitor Cpz 14. Two switches, switch S116 and switch S218, connect the transducer to VPP 10 and VSS 12 respectively. The polarity of a signal, called POL (polarity) 20, determines which power supply (VPP or VSS) is connected to the transducer 14. The output voltage (Vout) 22 across each transducer 14 should reach a specific level determined by a 6-bit data stored in a 6-bit latch 24 as shown in FIG. 1. This allows the voltage across each transducer 14 to be trimmed to a determined value in order to compensate for sensitivity variations of different transducers on the print head. This procedure is called “Normalization” or “Calibration”.
Referring once again to FIGS. 1 and 2, assuming that the print data is “1”, a signal call SEL (select) 26 goes high at time t128, switch S116 is closed connecting the output transducer 14 to VPP 10 and the output voltage (Vout) 22 across the transducer 14 follows VPP 10. VPP 10 has a high slope between t128 and t2 (fast slew) 30 and after t230 slope is lower for normalization purpose. At time t230, when the slope of VPP 10 is changed, a signal NOM_CEN (Normalization Counter Enable) 32 goes high and triggers a 6-bit counter 34. The output of the counter 34 is compared to the normalization data (B0B1B2B3B4B5) stored in the 6-bit latch 24 in the delay circuit 36 (shown in FIG. 2) and when it matches that data a signal called NORM_LATCH 38 goes low at time t340. So basically the delay circuit 36 generates a signal delayed from t230 and the amount of delay is determined by 6-bit data stored in 6-bit latch 24. At this time (t3) 40 the signal NORM_LATCH 38 is used to disconnect the output from VPP 10 and the capacitive load of the transducer 14 keeps the output voltage 22 at this level, so the voltage across the transducer 14 is adjusted by 6-bit normalization data.
At time t442 the POL (polarity) signal 20 goes low and switch S218 is closed connecting the transducer 14 to negative supply VSS 12 and Vout 22 follows VSS 12. Similarly at time t544 the slope of VSS 12 is changed and the 6-bit counter 34 is triggered again and at time t646, delayed from t544 based on normalization data B0B1B2B3B4B5, the transducer 14 is disconnected from VSS 12 and keeps its voltage at this level. As a result the output voltage 22 shown in FIG. 2 is generated across the transducer 14 which is basically shaped by the predetermined shapes of VSS 12 and VPP 10 and its amplitudes are adjusted by “normalization” data.